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? semiconductor components industries, llc, 2002 july, 2002 rev. 0 1 publication order number: nud3105/d nud3105 integrated relay, inductive load driver this device is used to switch inductive loads such as relays, solenoids incandescent lamps , and small dc motors without the need of a freewheeling diode. the device integrates all necessary items such as the mosfet switch, esd protection, and zener clamps. it accepts logic level inputs thus allowing it to be driven by a large variety of devices including logic gates, inverters, and microcontrollers. features ? provides a robust driver interface between d.c. relay coil and sensitive logic circuits ? optimized to switch relays from 3.0 v to 5.0 v rail ? capable of driving relay coils rated up to 2.5 w at 5.0 v ? internal zener eliminates the need of freewheeling diode ? internal zener clamp routes induced current to ground for quieter systems operation ? low v ds(on) reduces system current drain typical applications ? telecom: line cards, modems, answering machines, fax ? computers and office: photocopiers, printers, desktop computers ? consumer: tvs and vcrs, stereo receivers, cd players, cassette recorders ? industrial:small appliances, security systems, automated test equipment, garage door openers ? automotive: 5.0 v driven relays, motor controls, power latches, lamp drivers http://onsemi.com device package shipping ordering information nud3105lt1 sot23 3000 units/reels marking diagram relay, inductive load driver silicon smallblock 0.5 ampere, 8.0 v clamp 1 2 3 sot23 to236 case 318 internal circuit diagram drain (3) 1.0 k 300 k gate (1) source (2) jw4d jw4 = specific device code d = date code
nud3105 http://onsemi.com 2 maximum ratings (t j = 25 c unless otherwise specified) symbol rating value unit v dss drain to source voltage clamped v dc v gs gate to source voltage continuous clamped v dc i d drain current continuous 500 ma e z single pulse draintosource avalanche energy ( t jinitial = 25 c) (note 2) 50 mj e zpk repetitive pulse zener energy limit (dc 0.01%) (f = 100 hz, dc = 0.5) 4.5 mj t j junction temperature 150 c t a operating ambient temperature 40 to 85 c t stg storage temperature range 65 to +150 c p d total power dissipation (note 1) derating above 25 c 225 1.8 mw mw/ c r ja thermal resistance junctiontoambient 556 c/w 1. this device contains esd protection and exceeds the following tests: human body model 2000 v per mil_std883, method 3015 machine model method 200 v 2. refer to the section covering avalanche and energy and figure 12. typical electrical characteristics (t a = 25 c unless otherwise noted) symbol characteristic min typ max unit off characteristics v brdss drain to source sustaining voltage (internally clamped) (i d = 10 ma) 6.0 8.0 9.0 v b vgso i g = 1.0 ma 8.0 v i dss drain to source leakage current (v ds = 5.5 v , v gs = 0 v, t a = 25 c) (v ds = 5.5 v, v gs = 0 v, t a = 85 c ) 15 15 a i gss gate body leakage current (v gs = 3.0 v, v ds = 0 v) (v gs = 5.0 v, v ds = 0 v) 5.0 19 50 a on characteristics v gs(th) gate threshold voltage (v gs = v ds , i d = 1.0 ma) (v gs = v ds , i d = 1.0 ma, t a = 85 c) 0.8 0.8 1.2 1.4 1.4 v r ds(on) drain to source onresistance (i d = 250 ma, v gs = 3.0 v) (i d = 500 ma, v gs = 3.0 v) (i d = 500 ma, v gs = 5.0 v) (i d = 500 ma, v gs = 3.0 v, t a =85 c) (i d = 500 ma, v gs = 5.0 v, t a =85 c) 1.2 1.3 0.9 1.3 0.9 i ds(on) output continuous current (v ds = 0.25 v, v gs = 3.0 v) (v ds = 0.25 v, v gs = 3.0 v, t a = 85 c) 300 200 400 ma g fs forward transconductance (v out = 5.0 v, i out = 0.25 a) 350 570 mmhos dynamic characteristics c iss input capacitance (v ds = 5.0 v,v gs = 0 v, f = 1.0 mhz) 25 pf c oss output capacitance (v ds = 5.0 v, v gs = 0 v, f = 1.0 mhz) 37 pf
nud3105 http://onsemi.com 3 typical electrical characteristics (t a = 25 c unless otherwise noted) symbol unit max typ min characteristic dynamic characteristics c rss transfer capacitance (v ds = 5.0 v, v gs = 0 v, f = 1.0 mhz) 8.0 pf switching characteristics symbol characteristic min typ max units t phl t plh t phl t plh propagation delay times: high to low propagation delay; figure 1 (5.0 v) low to high propagation delay; figure 1 (5.0 v) high to low propagation delay; figure 1 (3.0 v) low to high propagation delay; figure 1 (3.0 v) 25 80 44 44 ns t f t r t f t r transition times: fall time; figure 1 (5.0 v) rise time; figure 1 (5.0 v) fall time; figure 1 (3.0 v) rise time; figure 1 (3.0 v) 23 32 53 30 ns figure 1. switching waveforms v out gnd v in gnd v z v cc v cc t r t f t plh t phl 50% 90% 50% 10%
nud3105 http://onsemi.com 4 typical characteristics v z , zener clamp voltage (v) v gs = 0 v 11.0 12.0 10.0 9.0 8.0 7.0 13.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 v ds , drain to source voltage (v) figure 2. output characteristics v ds , gatetosource voltage (v) figure 3. transfer function temperature ( c) figure 4. on resistance variation vs. temperature figure 5. r ds(on) variation with gatetosource voltage figure 6. zener voltage vs. temperature i z , zener current (ma) figure 7. zener clamp voltage vs. zener current i d , drain current (a) 50 25 0 25 50 75 100 1200 1000 800 600 400 200 0 125 r ds(on) , draintosource resistance (m ) v z , zener voltage (v) 50 25 0 25 50 75 100 125 i z = 10 ma i d = 0.25 a v gs = 3.0 v 50 c 1.0 1.2 1.4 1.6 0.8 50 45 40 35 30 25 20 2.0 15 1.8 r ds(on) , draintosource resistance ( ) i d = 250 a 1.0 10 0.1 100 v gs = 0 v v gs = 1.0 v i d , drain current (a) v gs = 5.0 v v gs = 3.0 v v gs = 2.0 v t j = 25 c 10 1.0 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 85 c 40 c v ds = 0.8 v i d = 0.5 a v gs = 3.0 v i d = 0.5 a v gs = 5.0 v v ds , gatetosource voltage (v) 50 c 85 c 40 c 125 c 8.20 8.18 8.16 8.14 8.12 8.10 8.08 8.06 8.04 8.02 8.00 temperature ( c) 10 1.0 0.1 0.01 0.001 0.0001 0.00001 85 c 40 c 25 c 25 c 25 c 1000 6.0
nud3105 http://onsemi.com 5 typical characteristics v ds , draintosource voltage (v) 0.01 100 10 0.1 0.1 1.0 0.01 i d , drain current (a) 1.0 r ds(on) limit thermal limit package limit i d , drain current (a) figure 8. onresistance vs. drain current and temperature temperature ( c) figure 9. gate leakage vs. temperature r ds(on) , draintosource resistance ( ) 1.0 0.9 0.8 0.5 0.6 0.7 1.1 1.2 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 i gss , gate leakage ( a) 30 25 0 5 10 35 40 50 25 0 25 50 75 100 125 20 15 125 c 85 c 50 c 25 c 40 c v gs = 3.0 v v gs = 5.0 v figure 10. safe operating area figure 11. transient thermal response 0.01 0.1 1.0 10 100 1000 10,000 100,000 1,000,000 d = 0.5 0.2 0.1 0.05 0.02 single pulse 0.01 p d(pk) t 1 t 2 duty cycle = t 1 /t 2 period pw r(t), transient thermal resistance (normalized) 1.0 0.1 0.01 0.001 t1, pulse width (ms) dc pw = 0.1 s dc = 50% pw = 7.0 ms dc = 5% pw = 10 ms dc = 20% typical i z vs. v z v (br)dss min = 6.0 v i dcontinuous = 0.5 a v gs = 3.0 v, t c = 25 c
nud3105 http://onsemi.com 6 avalanche energy the draintosource clamp, internal to the nud3105, is designed to protect the device during avalanche energy produced by a load such as an inductor or relay. in many cases, the upper limit of this clamp will be a function of the current through it and the draintosource breakdown voltage. the maximum material voltage of the nud3105 is between 12 and 13 volts. thus, as the breakdown exceeds 13 v, the device will fail due to the material voltage. this 12 v and 13 v on the clamp corresponds to a current through the clamp of 320 to 440 ma, respectively. the avalanche energy graph, given in figure 12, is actually limited by the material voltage and the clamp current. repetitive avalanche energy is based upon t j max, t a , r ja , transient thermal response, frequency and duty cycle. figure 12. avalanche energy eas, single pulse drainto source avalanche energy (mj) v cc = 5.0 v v cc = 3.0 v 60 50 40 30 20 10 0 50 100 150 200 250 300 350 inductor (mh) 00 inductor v cc + 3 2 1 3 1. gate 2. source 3. drain using ttr designing for pulsed operation for a repetitive pulse operating condition, time averaging allows one to increase a device's peak power dissipation rating above the average rating by dividing by the duty cycle of the repetitive pulse train. thus, a continuous rating of 200 mw of dissipation is increased to 1.0 w peak for a 20% duty cycle pulse train. however, this only holds true for pulse widths which are short compared to the thermal time constant of the semiconductor device to which they are applied. for pulse widths which are significant compared to the thermal time constant of the device, the peak operating condition begins to look more like a continuous duty operating condition over the time duration of the pulse. in these cases, the peak power dissipation rating cannot be merely time averaged by dividing the continuous power rating by the duty cycle of the pulse train. instead, the average power rating can only be scaled up a reduced amount in accordance with the device's transient thermal response, so that the device's max junction temperature is not exceeded. figure 11 of the nud3105lt1 data sheet plots its transient thermal resistance, r(t) as a function of pulse width in ms for various pulse train duty cycles as well as for a single pulse and illustrates this effect. for short pulse widths near the left side of the chart, r(t), the factor, by which the continuous duty thermal resistance is multiplied to determine how much the peak power rating can be increased above the average power rating, approaches the duty cycle of the pulse train, which is the expected value. however, as the pulse width is increased, that factor eventually approaches 1.0 for all duty cycles indicating that the pulse width is sufficiently long to appear as a continuous duty condition to this device. for the nud3105lt1, this pulse width is about 100 seconds. at this and larger pulse widths, the peak power dissipation capability is the same as the continuous duty power capability. to use figure 11 to determine the peak power rating for a specific application, enter the chart with the worst case pulse condition, that is the max pulse width and max duty cycle and determine the worst case r(t) for your application. then calculate the peak power dissipation allowed by using the equation, pd(pk) = (t jmax t amax ) (r ja * r(t)) pd(pk) = (150 c t amax ) (556 c/w * r(t)) thus for a 20% duty cycle and a pw = 40 ms, figure 10 yields r(t) = 0.3 and when entered in the above equation, the max allowable pd(pk) = 390 mw for a max t a = 85 c. also note that these calculations assume a rectangular pulse shape for which the rise and fall times are insignificant compared to the pulse width. if this is not the case in a specific application, then the v o and i o waveforms should be multiplied together and the resulting power waveform integrated to find the total dissipation across the device. this then would be the number that has to be less than or equal to the pd(pk) calculated above. a circuit simulator having a waveform calculator may prove very useful for this purpose.
nud3105 http://onsemi.com 7 information for using the sot23 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. sot23 mm inches 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 sot23 power dissipation the power dissipation of the sot23 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sot23 package, p d can be calculated as follows: p d = t j(max) t a r ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 225 milliwatts. p d = 150 c 25 c 556 c/w = 225 milliwatts the 556 c/w for the sot23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. there are other alternatives to achieving higher power dissipation from the sot23 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference should be a maximum of 10 c. ? the soldering temperature and time should not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient should be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
nud3105 http://onsemi.com 8 designing with this data sheet 1. determine the maximum inductive load current (at max v cc , min coil resistance & usually minimum temperature) that the nud3105 will have to drive and make sure it is less than the max rated current. 2. for pulsed operation, use the transient thermal response of figure 11 and the instructions with it to determine the maximum limit on transistor power dissipation for the desired duty cycle and temperature range. 3. use figures 10, 11 and 12 with the soa notes to insure that instantaneous operation does not push the device beyond the limits of the soa plot. 4. verify that the circuit driving the gate will meet the v gs(th) from the electrical characteristics table. 5. using the max output current calculated in step 1, check figure 7 to insure that the range of zener clamp voltage over temperature will satisfy all system & emi requirements. 6. use i gss and i dss from the electrical characteristics table to insure that aoffo state leakage over temperature and voltage extremes does not violate any system requirements. 7. review circuit operation and insure none of the device max ratings are being exceeded. figure 13. a 200 mw, 5.0 v dual coil latching relay application with 3.0 v level translating interface +4.5 v cc +5.5 vdc + v out (3) + v in (1) gnd (2) nud3105lt1 +3.0 v dd +3.75 vdc applications diagrams v out (3) v in (1) gnd (2) nud3105lt1
nud3105 http://onsemi.com 9 figure 14. a 140 mw, 5.0 v relay with ttl interface +4.5 to +5.5 vdc + v out (3) aromat tx25v max continuous current calculation for tx25v relay, r1 = 178 nominal @ r a = 25 c assuming 10% make tolerance, r1 = 178 * 0.9 = 160 min @ t a = 25 c t c for annealed copper wire is 0.4%/ c r1 = 160 * [1+(0.004) * (40 25 )] = 118 min @ 40 c i o max = (5.5 v max 0.25v) /118 = 45 ma + v out (3) aromat js1e5v figure 15. a quad 5.0 v, 360 mw coil relay bank + aromat js1e5v + aromat js1e5v + aromat js1e5v +4.5 to +5.5 vdc v in (1) gnd (2) nud3105lt1 v in (1) gnd (2) nud3105lt1
nud3105 http://onsemi.com 10 package dimensions case 31808 issue af sot23 (to236) d j k l a c b s h g v 3 1 2 dim a min max min max millimeters 0.1102 0.1197 2.80 3.04 inches b 0.0472 0.0551 1.20 1.40 c 0.0350 0.0440 0.89 1.11 d 0.0150 0.0200 0.37 0.50 g 0.0701 0.0807 1.78 2.04 h 0.0005 0.0040 0.013 0.100 j 0.0034 0.0070 0.085 0.177 k 0.0140 0.0285 0.35 0.69 l 0.0350 0.0401 0.89 1.02 s 0.0830 0.1039 2.10 2.64 v 0.0177 0.0236 0.45 0.60 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. style 6: pin 1. base 2. emitter 3. collector
nud3105 http://onsemi.com 11 notes
nud3105 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nud3105/d smallblock is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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